1. Field of the Invention
The present invention relates to electronic devices, and in particular, to under bump metallization and solder bumps for interconnection of electronic components.
2. Description of Related Art
In the microelectronics industry, surface mount technology (SMT) involves forming electronic package assemblies in which an electrical component, such as an integrated circuit chip, is electrically and mechanically connected to a substrate, a card (i.e., board), another chip or another electronic part. These multilayer electronic components are typically joined to each other by solder interconnections, such as C4 technology or flip chip packaging, or BGA (Ball Grid Array) interconnections. The solder interconnections join the pads on a first of these electronic components to corresponding pads on the surface of a second component, e.g., pads on a chip to corresponding pads on a substrate.
Conventional solder materials for soldering semiconductors to ceramic substrates include high melting point solder alloys having a high lead content. For instance, a preferred solder material for forming solder joints over the years has been a composition of 97 wt % lead (Pb) to 3 wt % tin (Sn). These lead containing solder joints are generally plated or evaporated solder on under bump metal (UBM) films. Typical UBM films for use with lead containing solders include an adhesion layer (e.g., TiW) followed by a diffusion barrier layer (e.g., CrCu) and then a capping or solder wettable layer (e.g., Cu). While such UBM film compositions provide adequate performance and reliability when used with lead containing solders, they are neither adequate nor reliable when used with lead-free solders as discussed below.
Over the years, due to the continually increasing costs and environmental factors, industry is shifting more towards the use of lead-free solders. Known lead-free solders for use in the semiconductor industry are generally tin-rich, such as, for example, tin-copper (Sn/Cu), tin-silver (Sn/Ag) or tin-silver-copper (Sn/Ag/Cu) solders. However, when these tin-rich solders are provided over the CrCu barrier layers, the high tin (Sn) content results in the rapid consumption of copper (Cu) from the CrCu UBM, leading to solder joint delamination. This high tin (Sn) content also reacts with the chromium (Cr) causing it to float to solder joint surfaces, which in turn, leads to non-wettable solder joints.
To avoid the above problems associated between CrCu barrier UBM layers and lead-free solder joints, nickel (Ni) or nickel vanadium (NiV) barrier UBM layers have replaced the CrCu barrier UBM layers. These Ni and NiV barrier UBM layers exhibit a slower reaction rate between Ni and Sn as compared to the reaction rate between Cu, or CrCu and Sn. Typically, the Ni UBM layers are electroless plated and NiV sputtered onto the adhesion layer. In so doing, electroless plated nickel phosphorous (EL-Ni—P) UBM layers are deposited to a thickness of about 2 to about 5 microns, while the sputtered Ni or NiV layers are deposited to a thickness of about 0.3 to about 0.5 microns.
While lower thicknesses of the EL-Ni—P or NiV UBM layers provide solutions for low-end applications, it does not meet the needs for high-end, high-performance applications. The process of depositing these layers by electroless plating incorporates P atoms in an EL-Ni—P layer or V atoms in NiV layers. However, it has been found that these impurities are undesirable in the barrier layer since the multiple solder reflows and thermal migration/diffusion of V impacts barrier consumption, and P atoms affecting the electromigration performance and reliability of C4 interconnections. The higher stresses in these EL-Ni—P or NiV layers may also detrimentally lead to fractures in the subsurface, which is commonly referred to in the industry as the “white bump” problem. Further, the conventional approaches for sputtering Ni or NiV provide UBM layers that are too thin, such that, they are completely consumed after about 4-5 reflows, each at about 250° C. to 260° C. for about 5 minutes. Sputtering these Ni or NiV layers too thick may also detrimentally result in higher stresses, for example, residual stresses in the range of 200 MPa to 600 MPa, which in turn, results in excessive wafer bowing causing difficulty in chucking and auto handling processes (e.g., for those wafers bowed at 600 microns or higher).
However, sputtering techniques continue to be preferred for present and future generations of UBM layers due to process simplicity, ease in process integration, cost effectiveness and the ability to overcome the performance limitations associated with Electroless plated Ni—P and sputtered NiV UBMs.